This invention relates generally to fabrication of silicon micro mechanical structures. More particularly, it relates to released microstructures made of sputtered silicon that are compatible with pre-fabricated on-chip aluminum circuitry.
Polysilicon has become the material of choice for most surface micro-machined structures due to its excellent mechanical properties and controllable stress. The commonly used process to deposit polysilicon is low pressure chemical vapor deposition (LPCVD), which requires relatively high deposition temperatures of 580-630xc2x0 C. and annealing temperatures above 900xc2x0 C. See for instance R. T. Hove and R. S. Muller, Abstract No. 118, Extended Abstracts of the Electrochemical Society Meeting, Montreal, Canada, May, 1982, pp. 184-185; or R. T. Howe and R. S. Muller, xe2x80x9cIntegrated Resonant-Microbridge Vapor Sensorxe2x80x9d Proc. IEEE Int. Elect. Dev. Mtg., San Francisco, December, 1984, pp. 213-216.
Since electronic circuitry is typically heat resistant only up to temperatures below those required for the LPCVD, re-engineering may have to be performed to bring pre-fabricated circuitry into operational condition unless the metal layers are deposition after the polysilicon deposition as is described for example in J. H. Smith, et al., xe2x80x9cEmbedded micromechanical devices for the monolithic integration of MEMS with CMOES,xe2x80x9d Proc. Int. Electron Devices Mtg., Washington, D.C., December, 1995, pp. 609-612.
Another alternative is to use refractory metals such as tungsten instead of aluminum as is described, for example in J. M. Bustillo, et al., xe2x80x9cProcess technology for modular integration of CMOS and polysilicon microstructures,xe2x80x9d Microsystem Technologies, Vol. 1, 1994, pp.30-41. These approaches increase the overall fabrication complexity.
The integration of microstructures and electronic circuitry is vital to the performance of many surface micro-machined sensors, since as dimensions decrease, sensitivity often falls off precipitously. The sensitivity of a torsional capacitive accelerometer, for example, scales with the fifth power of the lateral dimension of it.
Stresses and strain gradients can limit the performance of both integrated and passive electrostatic MEMS devices. If the in-plane residual stress in doubly supported structures, for example, is too large, the structures may buckle. Conversely, if the stresses are too large the mechanical stiffness may be too large for the intended application. Stress control in sputtered structures has been achieved previously with high temperature anneals as is described, for example, in T. Abe and M. L. Reed, xe2x80x9cLow Strain Sputtered Polysilicon for Micromechanical Structures,xe2x80x9d Proc. of Ninth International Workshop on Micro Electro-Mechanical Systems, San Diego February, 1996, pp. 258-262. These high temperature anneals ( greater than 1000xc2x0 C. exceed their thermal annealing budget critical thermal budgets of integrated circuitry. The critical thermal budget is the budget beyond which the configuration of the integrated circuitry becomes permanently changed.
The presence of strain gradients in deposited films causes released structures to warp. If the warpage is severe, the structures may touch the substrate, rendering them immobile. Alternatively, if the structures warp away from the substrate, capacitances of the structures diminish. Strain gradients result from initially sputtered silicon forming clusters on top of the sacrificial layer before reaching a closing thickness at which the sputtered silicon clusters have laterally extended and sufficiently overlapped to form a solid layer. The closing thickness is within several 100 Angstroms. The sputtered silicon within that closing thickness has a specific internal stress that differs significantly from the internal stress of the silicon deposited above the closing thickness. The phenomenon of the differing internal stress within the closing thickness is known to those skilled in the art as coalescence. The closing thickness is highly constant and introduces an essentially constant coalescence strain to the final structure. With increasing overall thickness of the micro-machined structure the influence of the coalescence strain becomes less influential. Depending upon the application, several additional properties may be important for the structural layer of a micro-fabricated device. Among these characteristics are film density, surface roughness and electrical resistivity, and permeability.
Thin layers of polysilicon are permeable to HF based etches as is described, for example, in K. S. Lebouitz, R. T. Howe, and A. P. Pisano, xe2x80x9cPermeable Polysilicon Etch-Access Windows for microshell Fabricationxe2x80x9d Transducres ""95, pp. 224-227. Unfortunately, the layer thickness useful for creating solid enclosed cavities are too thin for extended mechanical application and require additional reinforcing. layers. In particular, the capillary force of the etch requires a minimal thickness of the permeable layer to prevent a collapsing of the cavity cover. To prevent collapsing during wet etching, a critical point drying has to be performed, where the wet etch is frozen and then evaporated.
The inventive utilization of low temperature sputtering techniques for depositing silicon layers makes the use of organic materials for sacrificial layers possible. Such an organic material is preferably polyimide, which can be etched and removed by the use of a dry etch or dry plasma etch where capillary forces do not occur.
It is a primary object of the present invention to provide a micro-machined structure that can be fabricated non destructively to and in combination with pre-fabricated aluminum-metalized electronic circuitry.
It is another object of the present invention, to provide a method for making the micro-machined structure with tunable in-plane strain and strain gradient.
It is a further object of the present invention, to provide a micro-machined structure with predetermined levels of electric conductivity.
It is also an object of the present invention to provide a micro-machining process that employs a dry-release of the resultant micro-structure.
Finally, it is an object of the present invention, to provide a micro-machined structure with a porosity for creating encapsulated cavities with sufficiently thick cavity cover layers.
A sputtered layer is introduced. The sputtered layer, preferably from silicon, is deposited with predetermined sputtering criteria resulting in a predetermined pre-annealing configuration. This pre-annealing configuration is transformed during a low temperature annealing process into a post-annealing configuration. A released structure is micro-machined from the sputtered layer in its post-annealed configuration.
The fabrication process includes the initial deposition of a sacrificial layer, for example, phosphosilicate glass (PSG) or polyimide resin beneath the following layers predetermined for the released structure. The sacrificial layer is removed in a final fabrication step to the extent necessary to release the previously patterned structure.
The released structure has a resulting in-plane strain and a resulting strain gradient, which are predetermined in accordance with deformation configurations of the released structure. The deformation configuration depends on the shape of the released structure and on the fashion it is supported. The deformation configurations are distinguished between an essentially buckling-free deformation configuration and an essentially buckling-influenced deformation configuration. The buckling-free deformation configuration is, for example, a beam supported on one end. The buckling influenced deformation configuration is, for example a straight beam rigidly supported on both ends. In other words, the buckling-free deformation configuration is the case where the buckling principles according to Euler are not applicable; the buckling-influenced deformation configuration is the case where the buckling principles according to Euler have to be applied.
In the case, where a low temperature annealing is included in the fabrication of the released structure, the resulting in plane strain and the resulting strain gradient are only an initial in-plane strain and an initial strain gradient, which are transformed during the annealing into a residual in-plane and a residual strain gradient. Resulting in-plane strain/strain gradient and initial in-plane strain/strain gradient may differ, since the low temperature annealing allows an additional adjustment of them independently from the sputtering. Thus, sputtering criteria defined to deposit the silicon, may be more broadly selected when a low temperature annealing is included in the fabrication of micro-machined structures. The low temperature annealing is an optional fabrication step.
For buckling-free deformation configurations, first sputtering criteria predominantly include sacrificial layer etchant selection and sputtering layer thickness are defined such that the sputtered layer has a predetermined resulting or initial strain gradient. In the case, where a low temperature annealing is included in the fabrication process, the first sputtering criteria are selected in correlation with the annealing transformation.
For buckling-influenced deformation configurations, second sputtering criteria predominantly include and sacrificial layer material are defined such that the sputtered layer has a predetermined resulting or initial in-plane strain. Sputtering power, ambient sputtering pressure and sputtering temperature are selected from a zone-T of the Thornton zone diagram as known to those skilled in the art. In the case, where a low temperature annealing is included in the fabrication process, the second sputtering criteria are selected in correlation with the annealing transformation.
The low temperature annealing is performed with a thermal annealing budget, which includes sufficiently low maximum temperatures and sufficiently short annealing duration such that pre-fabricated integrated electronic circuitry is not permanently altered by the annealing. Thus, integrated electronic circuitry like, for example, aluminum-metalized circuitry or aluminum-metalized CMOS, can be fabricated and brought into operational condition on the same work piece or chip prior to the making of the micro-machined structure.
To adjust the electric conductivity of the micro-machined structure, a multi layer including a silicon core layer and at least one conductive layer with high electric conductivity are combined. The conductive layer has a dissolving characteristic that is compatible with the dissolving characteristic of the core layer. The dissolving characteristic includes an etching rate at which material of the multi layer structure is removed for a first group of etchants, selected to etch the multi layer structure. The dissolving characteristic includes further an etchant resistance against a second group of etchants, selected to etch the sacrificial layer. The compatible dissolving characteristic of the individual layers of the multi layer allows a simultaneous etch forming of the released structure from the multi layer. In the case where the core layer is made from silicon, the secondary layer(s) may be a Titanium based material such as TiW or TiN.
The sputtered layer made from silicon is porous and permeable to HF-based etches at approximately ten times the thicknesses reported for LPCVD deposited polysilicon. The initial porosity remains mostly unaltered during the annealing process such that encapsulated cavities with relatively thick cover layers may be fabricated compared to those made from polysilicon. Consequently, larger and/or more solid cover layers may be fabricated compared to those from prior art methods. *The cover layers are stiffer and better able to withstand the capillary forces of the wet etch in the encapsulated cavity beneath the silicon during a drying process. The annealing need not be performed prior to the release etching.